1. Field of the Invention
The present invention relates to a field of solid state switches and more specifically to control of their switching speeds.
2. Related Application
The present application is related to a copending U.S. patent application Ser. No. 005,942 filed Jan. 22, 1987 (U.S. Pat. No. 4,727,309) entitled "Current Difference Current Source" and is incorporated herein by reference to provide a teaching of such current source to be used in the compensated current source of the present invention.
3. Prior Art
In the design of solid state circuits and devices, controlling the switching characteristic of a device is a very desirable feature. It is well-known in the prior art that switching devices, such as transistors, draw higher peak current at faster switching speeds then at slower switching speeds. This difference is attributed to a change in the inherent properties of the device, as well as to a change in the external conditions, such as temperature and power supply voltage.
In a typical prior art transistor, higher peak current is encountered when switching at a faster rate in comparison to peak current encountered at a slower switching rate. Because these transistors are not compensated, they respond differently at faster switching conditions than at slower switching conditions and ideal or uniform responses are difficult to achieve at all switching conditions.
In the design of a certain circuit, such as oscillators, output buffers and delay lines, an appreciable variation in the switching speed introduced by changes in the external conditions and process variations present a difficult constraint to a designer. For example in a CMOS inverter, peak switching current depends on the electrical characteristic of switching transistors and the rise and fall times of input and output signals. Typically, the dominant transistor affecting the value of the peak switching current is the transistor that is charging or discharging the load capacitor during that particular transition.
In another example dealing with an output buffer, it has been the practice to design a device to provide predetermined parameters at the faster switching conditions. That is, maximum peak current and switching speed parameters were determined at the faster switching speed. The speed response occuring at the slower switching condition was typically a resulting response from the faster switching condition design. Further, output buffer devices suffered from ringing at higher speed switching conditions and provided poor low speed switching response.
Typically in the prior art, circuits were designed for a worst case condition and the performance of the circuit to other conditions were subject to variations of supply voltage, temperature, transistor process and saturation current. It is appreciated then that what is needed is a device that is capable of providing substantially uniform responses at all switching conditions, such that a more stable and controllable switching speeds are achieved.